[Submitted] Timing Calibration in Interleaved Current Steering DACs

Abstract

A feedback algorithm for removing timing mismatch problems and improving SNR of interleaved current steering DAC structures clocked at high frequency (in GHz) is proposed. The algorithm developed is tested to remove the timing errors at 4GHz frequency within a margin of 0.1% and improve the SNR by more than 24 dB and ENoB (Effective no. of bits) by more than 4 bits (SNR improvement can be more than 24 dB, depending upon the initial noise floor in the DAC output). The blocks have been designed using VerilogA. All the components used are also physically realizable at their operating frequency and the corresponding circuits have also been discussed. The calibration loop requires a bandwidth of only 20 MHz around the Nyquist frequency, where the input signal is not allowed. The feedback algorithm is able to complete the calibration within a period of 200ns. It consists of a bang-bang loop and there are oscillations at the final duty cycle of the output, due to the noise floor introduced by the ADC used in the loop.