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Raghav Chawla

Graphics Hardware Engineer

Intel Corporation

Biography

I am a CPU Engineer at SiFive, working majorly on Physical Design & RTL Optimization. I have been a part of some really interesting projects here so far. Previously, I have worked for Google & Intel.

On the side of fun, I like to cook for friends & family. Ever so often, I also like to write poems at YourQuote. Like every music wannabe, I bought a keyboard recently and am sluggishly learning to play it. On weekends, I can be found in a quiet corner at some literary event in Bangalore.

I graduated from IIT Roorkee in 2018, and have been in Bengaluru since then.

Interests

  • VLSI Physical Design
  • Computer Architecture
  • Device-Circuit co-design
  • Delay Characterization

Education

  • Bachelor with Honors in Electronics and Communication, 2018

    Indian Institute of Technology(IIT) Roorkee

Experience

 
 
 
 
 

CPU Physical Design

SiFive

Jan 2018 – May 2018 Roorkee, India
Part of OOO Cores Team, focusing on Load-Store Unit.
 
 
 
 
 

CPU Physical Design

Google Silicon

Jan 2018 – May 2018 Roorkee, India
Part of Google CPU Physical Design, focusing on Floating Point Unit convergence
 
 
 
 
 

Graphic Hardware Engineer

Intel Corporation

Jun 2018 – Present Bengaluru, India
  • Physical Design
  • Graphics Architectures
  • Performance Verification
 
 
 
 
 

Teaching Assistant

Dept. of ECE, IIT Roorkee

Jan 2018 – May 2018 Roorkee, India
Taught ‘Semiconductor Devices’, an introductory course for freshmen undergraduate students, for two semesters as Teaching Assistant for Dr. Anand Bulusu
 
 
 
 
 

Undergraduate Research Assistant

Dept. of ECE, IIT Roorkee

Jun 2017 – Apr 2018 Roorkee, India
Worked in Dr. Bulusu’s lab on developing an empirical delay model for cells under TSV stress in 3D ICs
 
 
 
 
 

RnD Trainee

ST Microelectronics

May 2017 – Aug 2016 Noida, India
Timing Caliberation algorithm for Interleaved current steering DACs

Publications

October 2019 IEEE ISCAS

[Submitted] Timing Calibration in Interleaved Current Steering DACs

A feedback algorithm for removing timing mismatch problems and improving SNR of interleaved current steering DAC structures clocked at high frequency (in GHz) is proposed. The algorithm developed is tested to remove the timing errors at 4GHz frequency within a margin of 0.1% and improve the SNR by more than 24 dB and ENoB (Effective no. of bits) by more than 4 bits

October 2018 IEEE S3S(San Fransisco)

TSV Induced Stress Model and Its Application in Delay Estimation

In this paper, we developed models to calculate the variation of threshold voltage and mobility due to stress around a TSV in 3D ICs. These models were then used to calculate delay variation of an inverter around a TSV.

Link
March 2018 IEEE ISDCS

Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structure

This paper presents a novel delay model for Inverter followed by Transmission Gate (Inv-Tx) structure. Our model is novel in the sense that it considers the series stack effect along with the internal node voltage and parasitic capacitances while treating the Inv-Tx structure as a single entity.

Link

Projects

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All Hardware AI & Software

Cell Delay modeling for TSV induced stress in 3D ICs

A holistic model to determine the threshold voltage and mobility changes around a TSV, and thus, delay through an inverter and a 2 input NAND gate. The final model needed coordinates of the cell to calculate the propagation delay.

Design of Analog Neuromorphic Circuits

Designed the circuit of a Pulse-Based Analog Velocity Sensor. Pixels were designed to detect the edge of an object using contrasting lights. Multiple pixels were then used to measure the velocity of a moving object.

Delay Modelling of a Static flip flop

A compact delay model to calculate delay through an Inverter-Transmission gate, considered as a single entity. Captured the effects of series stacking and parasitic capacitances while calculating delay.

Dynamic Speed Limit

A solution to the long impending problem of Traffic jams in Indian metro cities. The algorithm used a Machine Learning model with the continuity equation to determine the ideal traffic speed on different roads. Developed a working prototype to demonstrate the algorithm.

Propeller Clock

Developed a clock (Analog and Digital) using a rotating PCB consisting of a linear array of LEDs, based on the principle of the Persistence of Vision. The LEDs were set to light up at fixed delays so as to show the time precisely.

Timing Calibration Algorithm for Interleaved Current Steering DAC

A feedback algorithm for removing timing mismatch problems and improving SNR of interleaved current steering DAC structures clocked at high frequency (in GHz). The algorithm developed was tested to remove the timing errors at 4GHz frequency within a margin of 0.1% and improve the SNR by more than 24 dB and ENoB (Effective no. of bits) by more than 4 bits.

On Device Activity Recognition

An Activity-based Smart health assistant that can provide health tips, product recommendations etc by analyzing daily activities such as walking, sitting, standing etc. Developed using Smartphone’s accelerometer sensor, Machine learning (CNN).

I-V characteristic variations due to defects in CMOS

Studied different types of defects and the resulting shifting of bands. Simulated the corresponding changes in leakage current in MOSFET due to various forms of gate leakage and drain leakage.

Campus Buddy

Campus Buddy is an assistant which keeps you updated with the events and activities of student groups and helps you search Telephone Directory of IIT Roorkee.

Awards

Represented IIT Roorkee

Inter IIT Tech Meet Jan 2018
Represented IIT Roorkee in Inter IIT Tech Meet 2018 in the event- Engineers’ Conclave and won Silver Trophy overall

World Finalist

Valeo Innocation Challenge Oct 2017
Among Top 4 teams from all over the world in New Ways to Use Cars category

Best Aesthetic design award

Srishti, IIT Roorkee Mar 2016
Winner of the Best Aesthetic design award in Srishti 2016 (Annual Hobbies Club Exhibition, IIT Roorkee) for the project- Propeller Clock

National Finalist

IIT Bombay Feb 2016
Among Top 10 teams from all over India in Energy Section in Make In India hackathon

Winner of Social Hackathon

Sankalp, IIT Roorkee Feb 2015
Winner of the inter-college competition during Sankalp 2015 (Annual Social Convention, NSS, IIT Roorkee) for a mobile application on Women Security

Blog

Google Sideways

Paper Referred: Sideways: Depth-Parallel Training of Video Models Authors: Mateusz Malinowski, Grzegorz Świrszcz, João Carreira, and …
Last updated on May 10, 2020 5 min read

Analog Neuromorphic Velocity Sensor

Paper Referred: Pulse-Based Analog VLSI Velocity Sensors Authors: Jorg Kramer, Rahul Sarpeshkar, and Christof Koch Why this research? …
May 9, 2020 6 min read

Compression with Multi ECC Techniques

Paper Referred: Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories Authors: Irina Alam, Saptadeep Pal and …
Last updated on May 10, 2020 5 min read

Sparse Matrix Multiplication

Paper Referred: Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration Authors: Pareesa Ameneh …
Last updated on May 10, 2020 4 min read

A year at intel

I joined Intel in June 2018 and it feels just like yesterday. This journey has been full of technical learning and professional …
Last updated on Nov 12, 2019 2 min read

Presentations

Cell Delay Modeling for TSV induced stress in 3D ICs

IEEE IIT Roorkee Chapter Apr 2018

Dynamic Speed Limit

Valeo Innovation Challenge, France Oct 2017

Timing Calibration in Interleaved DACs

TR&D Department at STMicroelectronics Jul 2017

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